The HyperTransportÃ´ Technology Consortium, the nonprofit industry organization that manages the HyperTransport technology specification, today announced a major new release of the HyperTransport technology specification, the DirectPacket HyperTransport 1.1 Specification.
The new specification provides four new capabilities: native packet handling for efficient transport of user packets through board-level systems, a robust retry protocol for high reliability server and communications systems, peer-to-peer routing for direct connection between I/O devices, and three new sets of Virtual Channels including 16 channels optimized for streaming traffic. “These new capabilities make HyperTransport technology the most efficient means to stream large numbers of packets through a board level system,” said Gabriele Sartori, president of the HyperTransport Technology Consortium.
“HyperTransport technology, already firmly established in volume shipments in personal computers, servers, communications equipment and other high performance systems, is now perfectly positioned to meet the bandwidth and performance requirements of next generation systems that utilize packet-based data.”
“HyperTransport DirectPacket has the lowest overhead for packet-based traffic,” points out Brian Holden, Chair of the HyperTransport Technical Working Group that defined the new specification. Adds Holden, “Where other approaches provide overly complex specifications which impose a system-level architecture on their users, HyperTransport DirectPacket technology provides a streamlined, low-overhead solution for chip-to-chip packet transport at the board level. This approach provides low latency, highly efficient data paths, and allows OEMs to define their own system level architecture.”
“HyperTransport technology is a popular, low-cost, high-bandwidth I/O technology and these new specifications will enable communications equipment makers to easily utilize this technology in very high performance packet-based systems,” says Jag Bolaria, senior analyst at The Linley Group. “Being backward compatible with earlier versions of the specification is a plus, and the new peer-to-peer feature will enable more effective connections for those systems that don’t need legacy PCI device compatibility. The new Virtual Channels will simplify board-level integration with common communications protocols like SPI-4.2.”
HyperTransport DirectPacket technology was designed to support the needs of communications equipment, server and storage system makers when integrating board-level computing systems to high speed, packet-based I/O technologies.
The DirectPacket protocol is the most efficient way to move packet-based data traffic through board-level systems. It uses only 8 bytes of overhead for Write operations and 12 bytes of overhead for Read operations. In addition, the new peer-to-peer routing allows direct communication between HyperTransport-enabled devices without routing traffic through the attached host when PCI ordering is not required by the application.
Additional retry protocols were added to support next generation bus transfers speeds and to enable very high availability systems. Finally, a set of added channels operate in similar fashion to popular communications protocols such as SPI-4.2 and XAUI, making HyperTransport DirectPacket enabled systems easily bridged to those popular technologies.
About HyperTransportÃ´ Technology
HyperTransport technology is licensed on a royalty-free basis through the HyperTransport Technology Consortium. It is a universal chip-to-chip I/O connectivity technology that provides 12.8 Gigabyte/second bandwidth, frequency and width scalability, low-cost implementation and full software compatibility with the legacy Peripheral Component Interconnect (PCI) and PCI-X I/O technologies.
Enhanced 1.2V low-power LVDS signaling and dual-data rate data transfers deliver increased data throughput while minimizing signal crosstalk and EMI and reducing manufacturing costs. HyperTransport interconnect technology employs a packet-based data protocol to eliminate many sideband signals (control and command signals) and supports asymmetric, variable width data paths.
With over 50 HyperTransport technology-based products and services already announced, a Compatibility Program that ensures interoperability between devices, and the specification’s preservation of the vast software investments and infrastructure that already exist for PCI today, HyperTransport technology has established a significant footprint in a number of key market segments.
The HyperTransport product portfolio includes tunnel, bridge, graphic and switch chips from AMD, ALi, Alliance Semiconductor, NVIDIA, PLX Technology, and VIA Technologies; programmable-logic devices from Altera and Xilinx; processors and security processors from AMD, Broadcom, Cavium, Hifn, PMC-Sierra, and Transmeta; IP cores from Altera, GDA Technologies, Nurlogic, and Xilinx; BIOS software from AMI and Phoenix Technologies; verification and test tools from 0-In Design Automation, Agilent, FuturePlus, GDA Technologies, Schlumberger, Teradyne and TransEDA; and training courses and an architecture reference manual from Mindshare.
For a full product listing, please visit the HyperTransport Consortium’s web site at:hypertransport.org.